A semiconductor wafer generally includes a first or “front” side having integrated circuits formed thereon, and a backside comprising a thickness of a semiconductor material (e.g., silicon (Si), gallium arsenide (GaAs), or the like) either in a bulk Si/semiconductor wafer or a Si/semiconductor on insulator (SOI) package. Prior to the dicing and packaging of the individual integrated circuit chips, the backside of the wafer is typically thinned to remove unwanted semiconductor material.
There are several different bonding and wafer thinning processes that are currently used depending on the type of semiconductor substrate (e.g., SOI vs. bulk Si) or on the point in the process at which via are formed (i.e., before or after bonding). When using SOI substrates, the typical procedure temporarily bonds the first wafer die to a glass layer. The backside of the SOI wafer is then usually wet etched to an etch stop layer leaving the backside substrate around 1.8 μm thick. The etched wafer die is then bonded to another wafer, after which the glass layer is removed from the first wafer die. Once the multiple layers are bonded, via are formed to establish interlayer connections.
When bulk Si is used, one method begins with a first wafer die that includes back-end-of-the-line (BEOL) connections. This first wafer die is bonded to a surface of another wafer, after which the backside substrate is thinned. Once the thinning process is completed, via are then formed to establish interlayer connections.
A second method used in bulk Si wafers forms via before the bonding process. In this method, the first wafer die not only includes the active device connections, but also has the interconnecting via formed. After bonding to another wafer, the backside thinning works to expose backside connections to the pre-fabricated via.
The backside grinding process reduces the thickness of the integrated circuit chips, allows smaller packaging, provides better stress performance in laminated packages, and provides other known benefits. Existing control methods for backside grinding typically rely on the mechanical precision of the grinding tool to control the accuracy of the final thickness of the wafer. For ultra-thin three-dimensional (3D) integrated circuit (IC) wafers, the backside may be thinned to between 20-30 μm. Such thickness requirements may risk damage to the active device layer if the mechanism to determine material thickness during the backside grinding process is not accurate.
Existing methods for controlling the mechanical backside grinding process typically use a mechanical thickness dial gauge to identify the specific width or thickness for the grinding element to leave in tact. However, because the dial gauge itself is a mechanical process, its accuracy is intrinsically limited. FIGS. 1A-1C are cross-sectional diagrams illustrating a typical wafer grinding process. In FIG. 1A, semiconductor die 10, including, among other things, bulk Si 100, through Si via (TSV) 101, and passivation layer 102, is bonded to semiconductor die 11, including, among other things, bulk Si 104 and passivation layer 103. After semiconductor dies 10 and 11 are bonded together to form stacked die 12, as illustrated in FIG. 1B, processing machine 13 applies grinding surface 105 to grind away much of bulk Si 100 from stacked die 12. The thickness dial gauge (not shown) of processing machine 13 is set to stop grinding bulk Si 100 at a desired coarse thickness, typically between 50 and 30 μm.
Because the grinding process provides such a coarse grinding mechanism, the top most layer of Si of stacked wafer 12 is typically damaged, which generally prompts additional fine polishing to finish out the processing. Chemical mechanical polishing (CMP) or the like is usually performed over the damaged surface to create a more useful planarized surface in addition to more finely thinning stacked wafer 12. FIG. 1C illustrates processing machine 13 applying polishing surface 106 to continue finely thinning and repairing the top surface of stacked wafer 12. The CMP is continued until the thickness of bulk Si 100 reaches the desired amount, typically between 30 and 20 μm. Once this desired thickness is reached, TSV 101 is usually exposed for external connection to stacked wafer 12. During the CMP process, endpoint detection (EPD) is generally needed to detect the desired endpoint of the thinning. This EPD may be implemented through a time control (i.e., conducting CMP for a specified time which, in consideration of the polishing rate, should indicate a depth that the polishing will result in after the specified time). It may also be implemented through some kind of optical metrology, including optical microscopes (OM), infrared (IR) measurement, laser detection, or similar such optical measurement systems.
The precise control to implement the accuracy of the grinding/thinning process is, therefore, limited by the accuracy of the mechanical thickness dial, followed by complicated optical verification systems. If the dial cannot sufficiently control the exact depth desired, grinding may actually cross into an active device area potentially ruining the operability of the semiconductor device.
One method that was developed to overcome the problems in the grinding portion of wafer thinning is described in U.S. Patent Publication No.: 2005/0158889 by Brouillette, et al., (hereinafter “Brouillette”). Instead of relying on a mechanical thickness dial, the thickness of the semiconductor wafer is measured using optical metrology. Specifically, IR light is directed onto the semiconductor wafer. Based on the reflective and refractive properties of the semiconductor material, the system analyzes the reflected IR light wavelengths to determine the thickness of the wafer. However, while the Brouillette method provides wafer measurement without the use of physically-limited mechanical dials, the costs of the optical equipment is generally quite high. Moreover, the grinding process is typically halted each time an IR measurement is to take place. Therefore, the grinding process is slowed decreasing the overall though-put of the manufacturing process. Further still, because the grinding process is halted to perform the measurement, care is still warranted to prevent grinding into the active layers of the wafer between measurements.